1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile semiconductor storage device and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, LSIs are formed by integration of devices in a two-dimensional plane on the silicon substrate. Although the dimension for each device are commonly reduced (refined) to increase memory storage capacity, recent years are facing challenges in such refinement from the viewpoint of cost and technology. Such refinement requires further improvements in photolithography technology. However, the costs of lithography process are ever increasing. In addition, if such refinement is accomplished, it is assumed that physical improvement limit, such as in breakdown voltage between devices, would be reached unless driving voltage can be scaled. That is, it is likely that difficulties would be encountered in device operation itself.
Therefore, such semiconductor storage devices have been proposed recently where memory cells are arranged in a three-dimensional manner to achieve improved integration of memory devices (see, Patent Document 1: Japanese Patent Laid-Open No. 2007-266143).
One of the conventional semiconductor storage devices where memory cells are arranged in a three-dimensional manner uses transistors with a cylinder-type structure (Patent Document 1). Those semiconductor storage devices using transistors with the cylinder-type structure are provided with multiple conductive layers corresponding to gate electrodes and pillar-like columnar semiconductors. Interlayer insulation layers of silicon oxide (SiO2) are provided above and below respective conductive layers. Each columnar semiconductor layer serves as a channel (body) part of a respective transistor. Memory gate insulation layers are provided around the columnar semiconductor layers. Such a configuration including these conductive layers, columnar semiconductor layers, and memory gate insulation layers is referred to as a “memory string”.
However, in each memory string, the columnar semiconductor layer comprises polysilicon with little impurities. Thus, it is difficult to reduce the resistance of the columnar semiconductor layer to a desired value taking a leakage electric field from the conductive layers into consideration. That is, conventional techniques suffer from insufficient current in reading.
As such, attempts are made to reduce the resistance value of columnar semiconductor layers by reducing the film thickness of each interlayer insulation layer between respective conductive layers. However, another problem arises that the voltage in memory writing can exceed the breakdown voltage of the interlayer insulation layers. This means that an improved technology is desired that increases cell currents during read operation, while obtaining the breakdown voltage of the interlayer insulation layers.